High linearity CMOS variable gain amplifier for UWB applications

I. L. Abdalla; Y. A. Khalaf; F. A. Farag

doi:doi:10.11648/j.cssp.20120101.11

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High linearity CMOS variable gain amplifier for UWB applications

I. L. Abdalla, Y. A. Khalaf, F. A. Farag

Published in Science Journal of Circuits, Systems and Signal Processing (Volume 1, Issue 1)

Published: 30 December 2012

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Abstract

A large dynamic-range Programmable Variable Gain Amplifier (PVGA) suitable for Ultra Wide Band (UWB) applications is presented. The PVGA is composed of three programmable variable gain amplifier stages followed by an output buffer. Such wide bandwidth allows our proposed PVGA to be used in multi-standard protocols. Power reduction is developed for the variable gain amplifier stages. Thorough analyses of the mid-band gain and noise are presented; and design tradeoffs are carefully handled. The PVGA circuit is designed and simulated in 0.13 µm IBM-CMOS process; the overall PVGA with buffer consumes 25 mA from a 1.5 V supply. The PVGA achieves 54.5 dB dynamic-range (DR), 17.6 dBm IIP3, -42.31 dB THD at peak-to-peak differential output voltage of 1 V, and frequency 400 MHz Moreover; the pro-posed circuit reports a good noise performance; the average integrated noise is 121.6 nV/Hz at minimum gain of -0.5 dB.

Published in	Science Journal of Circuits, Systems and Signal Processing (Volume 1, Issue 1)
DOI	10.11648/j.cssp.20120101.11
Page(s)	1-8
Creative Commons	This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited.
Copyright	Copyright © The Author(s), 2012. Published by Science Publishing Group

Keywords

Automatic Gain Control (AGC), Variable Gain Amplifier (VGA), Programmable Variable Gain Amplifier (PVGA), Digitally-controlled Variable Gain Amplifier (DVGA), Buffer, CMOS Analog Integrated Circuits, Low Voltage, Wide Bandwidth

References

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APA Style

I. L. Abdalla, Y. A. Khalaf, F. A. Farag. (2012). High linearity CMOS variable gain amplifier for UWB applications. Science Journal of Circuits, Systems and Signal Processing, 1(1), 1-8. https://doi.org/10.11648/j.cssp.20120101.11

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ACS Style

I. L. Abdalla; Y. A. Khalaf; F. A. Farag. High linearity CMOS variable gain amplifier for UWB applications. Sci. J. Circuits Syst. Signal Process. 2012, 1(1), 1-8. doi: 10.11648/j.cssp.20120101.11

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AMA Style

I. L. Abdalla, Y. A. Khalaf, F. A. Farag. High linearity CMOS variable gain amplifier for UWB applications. Sci J Circuits Syst Signal Process. 2012;1(1):1-8. doi: 10.11648/j.cssp.20120101.11

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@article{10.11648/j.cssp.20120101.11,
  author = {I. L. Abdalla and Y. A. Khalaf and F. A. Farag},
  title = {High linearity CMOS variable gain amplifier for UWB applications},
  journal = {Science Journal of Circuits, Systems and Signal Processing},
  volume = {1},
  number = {1},
  pages = {1-8},
  doi = {10.11648/j.cssp.20120101.11},
  url = {https://doi.org/10.11648/j.cssp.20120101.11},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.cssp.20120101.11},
  abstract = {A large dynamic-range Programmable Variable Gain Amplifier (PVGA) suitable for Ultra Wide Band (UWB) applications is presented. The PVGA is composed of three programmable variable gain amplifier stages followed by an output buffer. Such wide bandwidth allows our proposed PVGA to be used in multi-standard protocols. Power reduction is developed for the variable gain amplifier stages. Thorough analyses of the mid-band gain and noise are presented; and design tradeoffs are carefully handled. The PVGA circuit is designed and simulated in 0.13 µm IBM-CMOS process; the overall PVGA with buffer consumes 25 mA from a 1.5 V supply. The PVGA achieves 54.5 dB dynamic-range (DR), 17.6 dBm IIP3, -42.31 dB THD at peak-to-peak differential output voltage of 1 V, and frequency 400 MHz Moreover; the pro-posed circuit reports a good noise performance; the average integrated noise is 121.6 nV/Hz at minimum gain of -0.5 dB.},
 year = {2012}
}

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TY  - JOUR
T1  - High linearity CMOS variable gain amplifier for UWB applications
AU  - I. L. Abdalla
AU  - Y. A. Khalaf
AU  - F. A. Farag
Y1  - 2012/12/30
PY  - 2012
N1  - https://doi.org/10.11648/j.cssp.20120101.11
DO  - 10.11648/j.cssp.20120101.11
T2  - Science Journal of Circuits, Systems and Signal Processing
JF  - Science Journal of Circuits, Systems and Signal Processing
JO  - Science Journal of Circuits, Systems and Signal Processing
SP  - 1
EP  - 8
PB  - Science Publishing Group
SN  - 2326-9073
UR  - https://doi.org/10.11648/j.cssp.20120101.11
AB  - A large dynamic-range Programmable Variable Gain Amplifier (PVGA) suitable for Ultra Wide Band (UWB) applications is presented. The PVGA is composed of three programmable variable gain amplifier stages followed by an output buffer. Such wide bandwidth allows our proposed PVGA to be used in multi-standard protocols. Power reduction is developed for the variable gain amplifier stages. Thorough analyses of the mid-band gain and noise are presented; and design tradeoffs are carefully handled. The PVGA circuit is designed and simulated in 0.13 µm IBM-CMOS process; the overall PVGA with buffer consumes 25 mA from a 1.5 V supply. The PVGA achieves 54.5 dB dynamic-range (DR), 17.6 dBm IIP3, -42.31 dB THD at peak-to-peak differential output voltage of 1 V, and frequency 400 MHz Moreover; the pro-posed circuit reports a good noise performance; the average integrated noise is 121.6 nV/Hz at minimum gain of -0.5 dB.
VL  - 1
IS  - 1
ER  -

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Author Information

I. L. Abdalla

Electronics and Communication, Egypt-Japan University for Science and Technology, Alexandria, Egypt
Y. A. Khalaf

Electronics and Communication, Zagazig University, Zagazig, Egypt
F. A. Farag

Electronics and Communication, Zagazig University, Zagazig, Egypt

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Plain Text BibTeX RIS

APA Style

I. L. Abdalla, Y. A. Khalaf, F. A. Farag. (2012). High linearity CMOS variable gain amplifier for UWB applications. Science Journal of Circuits, Systems and Signal Processing, 1(1), 1-8. https://doi.org/10.11648/j.cssp.20120101.11

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ACS Style

I. L. Abdalla; Y. A. Khalaf; F. A. Farag. High linearity CMOS variable gain amplifier for UWB applications. Sci. J. Circuits Syst. Signal Process. 2012, 1(1), 1-8. doi: 10.11648/j.cssp.20120101.11

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AMA Style

I. L. Abdalla, Y. A. Khalaf, F. A. Farag. High linearity CMOS variable gain amplifier for UWB applications. Sci J Circuits Syst Signal Process. 2012;1(1):1-8. doi: 10.11648/j.cssp.20120101.11

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@article{10.11648/j.cssp.20120101.11,
  author = {I. L. Abdalla and Y. A. Khalaf and F. A. Farag},
  title = {High linearity CMOS variable gain amplifier for UWB applications},
  journal = {Science Journal of Circuits, Systems and Signal Processing},
  volume = {1},
  number = {1},
  pages = {1-8},
  doi = {10.11648/j.cssp.20120101.11},
  url = {https://doi.org/10.11648/j.cssp.20120101.11},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.cssp.20120101.11},
  abstract = {A large dynamic-range Programmable Variable Gain Amplifier (PVGA) suitable for Ultra Wide Band (UWB) applications is presented. The PVGA is composed of three programmable variable gain amplifier stages followed by an output buffer. Such wide bandwidth allows our proposed PVGA to be used in multi-standard protocols. Power reduction is developed for the variable gain amplifier stages. Thorough analyses of the mid-band gain and noise are presented; and design tradeoffs are carefully handled. The PVGA circuit is designed and simulated in 0.13 µm IBM-CMOS process; the overall PVGA with buffer consumes 25 mA from a 1.5 V supply. The PVGA achieves 54.5 dB dynamic-range (DR), 17.6 dBm IIP3, -42.31 dB THD at peak-to-peak differential output voltage of 1 V, and frequency 400 MHz Moreover; the pro-posed circuit reports a good noise performance; the average integrated noise is 121.6 nV/Hz at minimum gain of -0.5 dB.},
 year = {2012}
}

Copy | Download

TY  - JOUR
T1  - High linearity CMOS variable gain amplifier for UWB applications
AU  - I. L. Abdalla
AU  - Y. A. Khalaf
AU  - F. A. Farag
Y1  - 2012/12/30
PY  - 2012
N1  - https://doi.org/10.11648/j.cssp.20120101.11
DO  - 10.11648/j.cssp.20120101.11
T2  - Science Journal of Circuits, Systems and Signal Processing
JF  - Science Journal of Circuits, Systems and Signal Processing
JO  - Science Journal of Circuits, Systems and Signal Processing
SP  - 1
EP  - 8
PB  - Science Publishing Group
SN  - 2326-9073
UR  - https://doi.org/10.11648/j.cssp.20120101.11
AB  - A large dynamic-range Programmable Variable Gain Amplifier (PVGA) suitable for Ultra Wide Band (UWB) applications is presented. The PVGA is composed of three programmable variable gain amplifier stages followed by an output buffer. Such wide bandwidth allows our proposed PVGA to be used in multi-standard protocols. Power reduction is developed for the variable gain amplifier stages. Thorough analyses of the mid-band gain and noise are presented; and design tradeoffs are carefully handled. The PVGA circuit is designed and simulated in 0.13 µm IBM-CMOS process; the overall PVGA with buffer consumes 25 mA from a 1.5 V supply. The PVGA achieves 54.5 dB dynamic-range (DR), 17.6 dBm IIP3, -42.31 dB THD at peak-to-peak differential output voltage of 1 V, and frequency 400 MHz Moreover; the pro-posed circuit reports a good noise performance; the average integrated noise is 121.6 nV/Hz at minimum gain of -0.5 dB.
VL  - 1
IS  - 1
ER  -

Copy | Download