Low Power Parallel Prefix Adder Design Using Two Phase Adiabatic Logic

Alireza Hassanzadeh; Ahmad Shabani

doi:doi:10.11648/j.jeee.20150306.11

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Low Power Parallel Prefix Adder Design Using Two Phase Adiabatic Logic

Alireza Hassanzadeh, Ahmad Shabani

Published in Journal of Electrical and Electronic Engineering (Volume 3, Issue 6)

Received: 24 October 2015 Accepted: 6 November 2015 Published: 7 December 2015

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Abstract

In this paper low power implementation of parallel prefix adders using two phase adiabatic logic has been investigated. A new structure has been proposed for the main blocks of parallel prefix adder. Three parallel prefix adders including Kogge-Stone, Brent-Kung and Ripple Carry have been considered. The effects of power clock frequency and loading capacitance on the new blocks have also been considered. Simulation results using 180nm technology parameters and trapezoidal waveform show an average of 34% power reduction in the main building blocks of the adder at 200MHz clock frequency. This power reduces to 54% for sine wave power clock waveform. This research suggests adiabatic implementation of parallel prefix adders for low power microprocessor and signal processing applications.

Published in	Journal of Electrical and Electronic Engineering (Volume 3, Issue 6)
DOI	10.11648/j.jeee.20150306.11
Page(s)	181-186
Creative Commons	This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited.
Copyright	Copyright © The Author(s), 2015. Published by Science Publishing Group

Keywords

Low Power, Adiabatic Logic, Parallel Prefix, 2PASCL

References

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[2]	A. K. Kumar, D. Somasundareswari, V. Duraisamy, and M. Pradeepkumar, "Low power multiplier design using complementary pass-transistor asynchronous adiabatic logic," International Journal on Computer Science and Engineering, vol. 2, pp. 2291-2297, 2010.
[3]	D. J. Willingham, "Asynchrobatic logic for low-power VLSI design," University of Westminster, 2010.
[4]	S. G. Younis, "Asymptotically zero energy computing using split-level charge recovery logic," Massachusetts Institute of Technology, 1994.
[5]	A. Kramer, J. S. Denker, S. C. Avery, A. G. Dickinson, and T. R. Wik, "Adiabatic computing with the 2N-2N2D logic family," in VLSI Circuits, Digest of Technical Papers, Symposium on, pp. 25-26, 1994.
[6]	A. K. Kumar, D. Somasundareswari, V. Duraisamy, and M. G. Nair, "Asynchronous adiabatic design of full adder using dual-rail domino logic," in Computational Intelligence & Computing Research (ICCIC), IEEE International Conference on, 2012, pp. 1-4.
[7]	H. Jianping, X. Tiefeng, and L. Hong, "A lower-power register file based on complementary pass-transistor adiabatic logic," IEICE transactions on information and systems, vol. 88, pp. 1479-1485, 2005.
[8]	M. Cutitaru and L. Belfore, "A partially-adiabatic energy-efficient logic family as a power analysis attack countermeasure," in Signals, Systems and Computers, 2013 Asilomar Conference on, 2013, pp. 1125-1129.
[9]	M. Cutitaru and L. A. Belfore II, "New Single-Phase Adiabatic Logic Family," in Proceedings of the International Conference on Computer Design (CDES), pp. 9-14, 2012.
[10]	N. Anuar, Y. Takahashi, and T. Sekine, "4-bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: a comparison with static CMOS," Proc. IEEE ECCTD, pp. 65-68, 2009.
[11]	N. Anuar, Y. Takahashi, and T. Sekine, "Adiabatic logic versus CMOS for low power applications," in ITC-CSCC: International Technical Conference on Circuits Systems, Computers and Communications, pp. 302-305, 2009.
[12]	A. Kramer, J. S. Denker, B. Flower, and J. Moroney, "2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits," in Proceedings of the 1995 international symposium on Low power design, pp. 191-196., 1995.
[13]	S. Kim and M. C. Papaefthymiou, "True single-phase adiabatic circuitry," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 9, pp. 52-63, 2001.
[14]	K. Takahashi and M. Mizunuma, "Adiabatic dynamic CMOS logic circuit," Electronics and Communications in Japan (Part II: Electronics), vol. 83, pp. 50-58, 2000.
[15]	R. P. Brent and H.-T. Kung, "A regular layout for parallel adders," 1979.
[16]	R. E. Ladner and M. J. Fischer, "Parallel prefix computation," Journal of the ACM (JACM), vol. 27, pp. 831-838, 1980.
[17]	W. N. HE, CMOS VLSI Design: A Circuits and Systems Perspective, 3/E: Pearson Education India, 2006.

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APA Style

Alireza Hassanzadeh, Ahmad Shabani. (2015). Low Power Parallel Prefix Adder Design Using Two Phase Adiabatic Logic. Journal of Electrical and Electronic Engineering, 3(6), 181-186. https://doi.org/10.11648/j.jeee.20150306.11

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ACS Style

Alireza Hassanzadeh; Ahmad Shabani. Low Power Parallel Prefix Adder Design Using Two Phase Adiabatic Logic. J. Electr. Electron. Eng. 2015, 3(6), 181-186. doi: 10.11648/j.jeee.20150306.11

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AMA Style

Alireza Hassanzadeh, Ahmad Shabani. Low Power Parallel Prefix Adder Design Using Two Phase Adiabatic Logic. J Electr Electron Eng. 2015;3(6):181-186. doi: 10.11648/j.jeee.20150306.11

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@article{10.11648/j.jeee.20150306.11,
  author = {Alireza Hassanzadeh and Ahmad Shabani},
  title = {Low Power Parallel Prefix Adder Design Using Two Phase Adiabatic Logic},
  journal = {Journal of Electrical and Electronic Engineering},
  volume = {3},
  number = {6},
  pages = {181-186},
  doi = {10.11648/j.jeee.20150306.11},
  url = {https://doi.org/10.11648/j.jeee.20150306.11},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.jeee.20150306.11},
  abstract = {In this paper low power implementation of parallel prefix adders using two phase adiabatic logic has been investigated. A new structure has been proposed for the main blocks of parallel prefix adder. Three parallel prefix adders including Kogge-Stone, Brent-Kung and Ripple Carry have been considered. The effects of power clock frequency and loading capacitance on the new blocks have also been considered. Simulation results using 180nm technology parameters and trapezoidal waveform show an average of 34% power reduction in the main building blocks of the adder at 200MHz clock frequency. This power reduces to 54% for sine wave power clock waveform. This research suggests adiabatic implementation of parallel prefix adders for low power microprocessor and signal processing applications.},
 year = {2015}
}

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TY  - JOUR
T1  - Low Power Parallel Prefix Adder Design Using Two Phase Adiabatic Logic
AU  - Alireza Hassanzadeh
AU  - Ahmad Shabani
Y1  - 2015/12/07
PY  - 2015
N1  - https://doi.org/10.11648/j.jeee.20150306.11
DO  - 10.11648/j.jeee.20150306.11
T2  - Journal of Electrical and Electronic Engineering
JF  - Journal of Electrical and Electronic Engineering
JO  - Journal of Electrical and Electronic Engineering
SP  - 181
EP  - 186
PB  - Science Publishing Group
SN  - 2329-1605
UR  - https://doi.org/10.11648/j.jeee.20150306.11
AB  - In this paper low power implementation of parallel prefix adders using two phase adiabatic logic has been investigated. A new structure has been proposed for the main blocks of parallel prefix adder. Three parallel prefix adders including Kogge-Stone, Brent-Kung and Ripple Carry have been considered. The effects of power clock frequency and loading capacitance on the new blocks have also been considered. Simulation results using 180nm technology parameters and trapezoidal waveform show an average of 34% power reduction in the main building blocks of the adder at 200MHz clock frequency. This power reduces to 54% for sine wave power clock waveform. This research suggests adiabatic implementation of parallel prefix adders for low power microprocessor and signal processing applications.
VL  - 3
IS  - 6
ER  -

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Author Information

Alireza Hassanzadeh

ECE Dept., Shahid Beheshti University, Tehran, Iran
Ahmad Shabani

ECE Dept., Shahid Beheshti University, Tehran, Iran

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APA Style

Alireza Hassanzadeh, Ahmad Shabani. (2015). Low Power Parallel Prefix Adder Design Using Two Phase Adiabatic Logic. Journal of Electrical and Electronic Engineering, 3(6), 181-186. https://doi.org/10.11648/j.jeee.20150306.11

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ACS Style

Alireza Hassanzadeh; Ahmad Shabani. Low Power Parallel Prefix Adder Design Using Two Phase Adiabatic Logic. J. Electr. Electron. Eng. 2015, 3(6), 181-186. doi: 10.11648/j.jeee.20150306.11

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AMA Style

Alireza Hassanzadeh, Ahmad Shabani. Low Power Parallel Prefix Adder Design Using Two Phase Adiabatic Logic. J Electr Electron Eng. 2015;3(6):181-186. doi: 10.11648/j.jeee.20150306.11

Copy | Download

@article{10.11648/j.jeee.20150306.11,
  author = {Alireza Hassanzadeh and Ahmad Shabani},
  title = {Low Power Parallel Prefix Adder Design Using Two Phase Adiabatic Logic},
  journal = {Journal of Electrical and Electronic Engineering},
  volume = {3},
  number = {6},
  pages = {181-186},
  doi = {10.11648/j.jeee.20150306.11},
  url = {https://doi.org/10.11648/j.jeee.20150306.11},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.jeee.20150306.11},
  abstract = {In this paper low power implementation of parallel prefix adders using two phase adiabatic logic has been investigated. A new structure has been proposed for the main blocks of parallel prefix adder. Three parallel prefix adders including Kogge-Stone, Brent-Kung and Ripple Carry have been considered. The effects of power clock frequency and loading capacitance on the new blocks have also been considered. Simulation results using 180nm technology parameters and trapezoidal waveform show an average of 34% power reduction in the main building blocks of the adder at 200MHz clock frequency. This power reduces to 54% for sine wave power clock waveform. This research suggests adiabatic implementation of parallel prefix adders for low power microprocessor and signal processing applications.},
 year = {2015}
}

Copy | Download

TY  - JOUR
T1  - Low Power Parallel Prefix Adder Design Using Two Phase Adiabatic Logic
AU  - Alireza Hassanzadeh
AU  - Ahmad Shabani
Y1  - 2015/12/07
PY  - 2015
N1  - https://doi.org/10.11648/j.jeee.20150306.11
DO  - 10.11648/j.jeee.20150306.11
T2  - Journal of Electrical and Electronic Engineering
JF  - Journal of Electrical and Electronic Engineering
JO  - Journal of Electrical and Electronic Engineering
SP  - 181
EP  - 186
PB  - Science Publishing Group
SN  - 2329-1605
UR  - https://doi.org/10.11648/j.jeee.20150306.11
AB  - In this paper low power implementation of parallel prefix adders using two phase adiabatic logic has been investigated. A new structure has been proposed for the main blocks of parallel prefix adder. Three parallel prefix adders including Kogge-Stone, Brent-Kung and Ripple Carry have been considered. The effects of power clock frequency and loading capacitance on the new blocks have also been considered. Simulation results using 180nm technology parameters and trapezoidal waveform show an average of 34% power reduction in the main building blocks of the adder at 200MHz clock frequency. This power reduces to 54% for sine wave power clock waveform. This research suggests adiabatic implementation of parallel prefix adders for low power microprocessor and signal processing applications.
VL  - 3
IS  - 6
ER  -

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